1. Field of the Invention
This invention relates to non-volatile semiconductor memories such as EEPROM and flash EPROM which uses negative control gate voltages.
2. Description of Related Art
Non-volatile semiconductor memory such as flash EPROM (electrically programmable read only memory) and EEPROM (electrically erasable programmable read only memory) commonly employ memory cells containing floating gate transistors that trap charge on floating gates. The trapped charge controls the memory cell's threshold voltage and indicates the value of a bit of data. The memory cell is read by sensing whether the cell conducts when a read voltage is applied to the cell's control gate. If the read voltage is greater than the threshold voltage, the memory cell conducts.
For a typical memory cell in an EEPROM or flash EPROM, the trapped charge and the threshold voltage of a memory cell are changed (programmed or erased) by creating a voltage difference between the control gate and an active region in an underlying substrate. The voltage difference attracts electrons to or repels electrons from the floating gate. For example, grounding a control gate and applying 15 volts to a drain of a typical N-channel floating gate transistor causes electron tunnelling from the floating gate to the drain and decreases the floating gate transistor's threshold voltage.
Some flash EPROMs apply a negative control gate voltage (less than a substrate's operating voltage) to decrease a memory cell's threshold voltage and apply a positive control gate voltage (greater than the substrate's operating voltage) to raise the memory cell's threshold voltage. Negative voltages are often provided by a negative voltage charge pump shown in FIG. 1A. In the charge pump of FIG. 1A, a periodic positive voltage signal PHI shown in FIG. 1B is applied to terminals 101 and 103 of capacitors 111 and 113 respectively, and a periodic positive voltage signal PHIB which is 180.degree. out of phase with signal PHI is applied to terminals 102 and 104 of capacitors 112 and 114 respectively. When voltage signal PHI is high (at supply voltage Vcc typically 3 or 5 volts), the voltage at a terminal 131 of capacitor 111 increases in a manner characteristic of an RC circuit. Current flows through diode 121 to ground, and negative charge collects on terminal 131. When voltage signal PHI falls to ground (0 volts), positive charge flows away from a terminal 101 of capacitor 111, but diode 121 restricts current at terminal 131. A negative voltage develops at terminal 131. The next time voltage signal PHI is high, the voltage at terminal 131 increases but not as high as before because more negative charge builds up at terminal 131. In a similar manner, a negative charge and potential builds up at terminals 132, 133, and 134. Because signals PHI and PHIB are out of phase, voltage at terminal 132 is highest when voltage a terminal 131 is lowest. Current through diode 122 lowers the highest voltage at terminal 132 to near lowest voltage at terminal 131. Diodes 123, 124, and 125 similarly keep terminals 133 to 135 at progressively more negative voltages.
Control of both positive and negative voltages in conventional integrated circuits (ICs) presents isolation problems. For example, a positive voltage reverse biases a junction between an N type region and a P type substrate, but a negative voltage on the N type region forward biases the junction causing current leaks between the N type region and the P type substrate. Accordingly, special isolation wells surrounding N type regions are employed to prevent currents when a negative voltage is applied. Forming isolation wells increases the number of processing steps, the size, and the cost of an IC.
Alternatively, isolation circuits prevent application of negative voltage to N type regions. To minimize the amount of isolation circuitry in a memory, typically, all control gates in a memory array are isolated as a block, and negative voltage is simultaneously applied to the control gates of all memory cells in the array. For flash EPROM, the block of memory cells are simultaneously erased by lowering their threshold voltages. To do this, a positive voltage is applied to the drains of memory cells in the block while the control gate voltage is negative.
In EEPROM, each memory cell is individually programmable by lowering its threshold voltage. Applying negative voltage to all of the control gates in the array is undesirable because applying negative voltages to blocks of memory cells may disturb the threshold voltages of unselected memory cells, and repeated application of negative voltages may disturb the charge enough to erroneously change data. Additionally, the combined capacitance of the control gates of a block of memory cells is relatively large. The large capacitance requires a large negative voltage charge pump to charge the control gates quickly, otherwise charging the control gates and reducing the threshold voltage of the selected memory cells takes a long time.
It would be desirable to apply negative voltage to a smaller number of memory cells, for example only to a selected row containing a selected memory cell, but the prior art fails to provide circuits which can be economically integrated into a memory array to apply negative voltages to selected rows.